1. Field of the Invention
This invention relates to analog and digital processors and methods, and more particularly to analog and digital circuits, systems, and methods for charge coupled devices (CCDs), CMOS imagers, and cameras.
2. Description of the Related Art
Charge coupled device (CCD) camera systems are configured to capture signals according to many different CCD output formats and pixel configurations. One such CCD camera includes a sensor array, a high voltage CCD driver for driving the sensor array, and a DC-DC converter. The sensor array drives an analog processor which is in turn connected to a digital processor. The analog processor converts the signals received from the sensor array from an analog form into digital data. Such a camera produces a digital still image with up to 8 k×8 k pixels. The sensor array includes a grid of sensing elements arranged in a plurality of lines distributed across a vertical axis. Each line has a predetermined horizontal width. The CCD sensor array requires vertical and horizontal timing signals. Current CCD systems fail to have analog processors which are able directly to provide both analog and vertical timing systems to the CCD array. This makes it technically difficult to control the timing of a CCD array.
Further, many CCD arrays require the provision of several control currents to enable operation of the CCD array. Provision of there control currents is difficult to implement technically with the digital processing circuitry used to operate and control the associated CCD arrays. Accordingly, it is desirable to enable the convenient and controllable provision of desired control currents to a CCD array.
Many analog processors used with CCD systems use analog-to-digital converters having a limited dynamic range. Therefore, there is a need for a processor to have an extended dynamic range to be able to process the CCD output into digital formatted data to enable user controlled hardware or software data processing leading to production of viewable digital images.
There is a further need to control output resolution of the analog and digital subsystems in terms of bit-width. According to one known CCD format, in order to obtain a still image with acceptable resolution and contrast from a CCD, a minimum of 10 bits of resolution is desired. To practically capture a CCD image, the data read-out time from the CCD is very limited. Accordingly, one such front end interface which accepts CCD data for conversion into digital form operates typically up to 16 MHz with a 10-bit analog-to-digital converter. Such a camera can produce a digital still image with up to 8 k×8 k pixels.
The feature set available in known CCD camera systems is increasing to include enhanced functionality, as well as extended dynamic range. Such extended functionality comes at a price in terms of electronic complexity and power consumption. For example, some current camera systems include a liquid crystal display (LCD) screen to enable viewing of images in a real-time viewfinder. This requires the CCD and associated processing chips to run in a video mode and to remain powered up while the screen is in use. This can dissipate a large amount of power that tends to shorten battery life. In such an operational mode, front end circuitry is operated at a resolution level which is unnecessary for driving the relatively low resolution LCD display, thereby consuming power needlessly. Accordingly, there is a need to enable low power operation of the analog and digital subsystems in CCD camera and imager systems that convert analog data into digital signal forms for user applications. There is a further need for low power operation of analog and digital subsystems generally that convert analog data into digital signal forms.